1. Field of the Invention
The invention relates to a semiconductor manufacturing process, and more particularly, to a process using a hard mask comprising metal during a semiconductor process.
2. Description of the Prior Art
With the progress of the semiconductor industry, the devices of integrated circuits have been reduced in size under sub-micron for development and design of high-density integrated circuits. In semiconductor manufacturing processes, mask technology is frequently utilized.
For example, integrated circuit fabrication on semiconductor structures for ultra scale integration (ULSI) requires multiple levels of metal interconnections for electrically connecting the miniaturized semiconductor devices. To overcome difficulties in fabricating metal interconnection in multi-layer, the damascene structure has been extensively researched and developed. In addition, because the resistive coefficient of copper is lower than that of other metals, such as aluminum, and copper has the advantage of better electro-migration resistance while low-k material effectively reduces resistance-capacitance (RC) delay effects between metal interconnections, single copper damascene structure and copper damascene structure have been widely used in fabrication of integrated circuits. Accordingly, the copper damascene process is taken as the technique that can solve metal interconnection problem of deep sub-half micro integrated circuits in the future.
In the damascene interconnect structure, a dielectric layer is defined to an electric circuit pattern by etching and copper is filled into recesses of the pattern. FIGS. 1 and 2 are schematic, cross-sectional diagrams showing a conventional partial-via-first dual damascene process. As shown in FIG. 1, a substrate 1 having thereon a base layer or a lower low-k dielectric layer 10 is provided. A lower copper wiring 12 is inlaid into the lower low-k dielectric layer 10. The lower copper wiring 12 and the low-k dielectric layer 10 are covered with a lower cap layer 14, usually made of nitrogen-doped silicon carbide (SiCN). A low-k dielectric layer 16, a silicon oxide cap layer 18, a hard mask layer 20, and a bottom anti-reflective coating (BARC) layer are sequentially deposited on the lower cap layer 14. A layer of photoresist (not shown) having a trench opening therein is formed on the BARC layer for defining the trench pattern of the damascene conductive line. Subsequently, a dry etching process is carried out. A trench recess 44 is etched into the hard mask layer 20 and the silicon oxide cap layer 18 through the trench opening. The dry etching stops on the silicon oxide cap layer 18. The remaining photoresist and BARC layer are then stripped off to expose the remaining hard mask 20. Thereafter, another BARC layer 38 is coated over the substrate 1 and fills the trench recess 44. A layer of photoresist 39 is then formed on the BARC layer 38. The photoresist layer has a via opening 42 patterned by using conventional lithographic methods. The via opening 42 is situated directly above the trench recess 44. Thereafter, using the photoresist layer 39 as an etching hard mask, the BARC layer 38, the silicon oxide cap layer 18, and the low-k dielectric layer 16 are etched through the via opening 42, thereby forming a partial via 46 in an upper portion of the dielectric layer 16.
Subsequently, as shown in FIG. 2, the remaining photoresist layer 39 and the BARC layer 38 are stripped off by using oxygen plasma, thereby exposing the remaining hard mask layer 20. Using the hard mask layer 20 as an etching hard mask, a dry etching is performed to etch away the exposed silicon oxide cap layer 18 and the low-k dielectric layer 16, simultaneously through the partial via 46 and continuously to etch the low-k dielectric layer 16, to convert the pattern of trench recess 44 and partial via 46 to the low-k dielectric layer 16, thereby forming a dual damascene opening 22 comprising a trench opening 24 and a via opening 26. This dry etching stops on the lower cap layer 14. Thereafter, a so-called liner removal step or LRM step is carried out to remove the exposed lower cap layer 14 from the via opening 26, thereby exposing the lower copper wiring 12. The subsequent steps for forming an upper damascene wiring structure including, for example, deposition of barrier and plating of copper are known in the art and are therefore omitted. The aforesaid etching step to remove cap layer 14 usually uses a plasma source comprising hydrogen-containing carbon fluoride such as CH2F2 or CHF3.
However, using a fluoroalkane plasma, such as CH2F2 or CHF3 plasma, to remove the cap layer 14 in the aforesaid etching step may lead to a process defect due to the formation of titanium-fluorine compound precipitates on the substrate surface through the reaction of fluorine radicals with the titanium contained in the hard mask. It is not desired and is a problem needed to solve.
Therefore, there is till a need for a better semiconductor manufacturing method to solve the problem that precipitates form on the substrate when a hard mask comprising titanium is used and fluorine radicals are remained.